Random access memory (RAM) is a ubiquitous component of modern digital architectures. RAM can be stand alone devices or can be integrated or embedded within devices that use the RAM, such as microprocessors, microcontrollers, application specific integrated circuits (ASICs), system-on-chip (SoC), and other like devices as will be appreciated by those skilled in the art.
Conventional integrated circuit memory architectures such as single ported memory, dual-ported memory and Content Addressable Memory (CAM), provide only one dimension of data word addressing space/organization. For example, a simple memory containing four words addressable linearly (i.e., one dimension only) either 0, 1, 2 or 3 is illustrated in FIG. 1A. The memory access via conventional integrated circuit memory architectures is limited to either read or write the selected (addressed) 4-bit word 110, as illustrated. If an application requires that bit 2 of the word 0, 1, 2 and 3 are read/written (e.g., 120 in FIG. 1B), four memory access cycles will be required. For example, in conventional single potted memory, all 4 words can be read/written but each bit will still be in the respective row it is read/written. Additional operations (e.g., shifting, masking, etc.) will be required, to manipulate the bits to obtain the individual bit information, as will be appreciated by those skilled in the art.
Many high performance applications such as signal processing, audio and video encoding/decoding, and the like use data stored in bit patterns that are not limited to the conventional word arrangements. Accordingly, it would be beneficial to have a memory architecture optimized for random matrix operations.